The present invention relates to an embedded testing circuit of a dual port memory and, more particularly, to a testing circuit embedded in a semiconductor integrated circuit together with a dual port memory for testing the memory.
In a dual port memory, for example in a dual port RAM having two systems each of address inputs 3a, 3b (AA0 . . . AAm, BA0 . . . BAm), data inputs 1a, 1b (AI0 . . . AIn, BI0 . . . BIn), and data outputs 2a, 2b (AO0 . . . AOn, BO0 . . . BOn), as shown in FIG. 1, the ports A and B are adapted to operate independently. However, it is prohibited to write different values to the same address from both of the ports.
As to the test of such a dual port RAM, it may be simply considered enough if read and write can be made from both of the ports A and B. However, a test to simultaneously read or write from both the ports is indispensable for checking specifications and analog behavior of the memory.
In a test of a dual port RAM, if a conventional test circuit of a single port RAM, in which a pattern of M-sequence (maximum length linearly recurring sequence) as it is is employed as the test pattern, is applied to the dual port RAM, then, it occurs that the M-sequence pattern is input to the address inputs 3a, 3b (AA0 . . . AAm, BA0 . . . BAm) and data inputs 1a, 1b (AI0 . . . AIn, BI0 . . . BIn) being sequentially shifted as shown in FIG. 2.
In that case, since the number of degrees of the M-sequence is determined by the maximum address space of ROM/RAM within the chip, it is not always assured that the number of degrees is matching with the address inputs to the RAM. Accordingly, in a write cycle, inputting to the same address from both the ports A and B can take place. Hence, the conventional means as it is cannot be employed.
Further, supposing that the M-sequence pattern is employed, if attention is paid to a specific memory cell, the following situations arise:
(1) the order of writing, i.e., whether data is written first from the port A and then from the port B or in the other way, cannot be controlled; and PA1 (2) while it is confirmed that data "1" can be written from the port B only when the data "1" is written from the port B after data "0" has been written from the port A, it is not assured that data are input in such sequence. Thus, there has been a problem that a sufficient test of a dual port RAM cannot be made by applying only the conventional test as it is to the dual port RAM.
In the M-sequence, when it is of a degree of n in general, the continuing binary values of n bits are all different, i.e., all the values from 0 to 2.sup.n -1 can be provided. An instance of 4-degree M-sequence signals is shown in FIG. 3. Here, i represents integers from 0 to 15, and A(i) corresponding to the integer i, represented by A(0) to A(15), indicates the data corresponding to A(i) (the M-sequence pattern). As apparent from FIG. 3, the binary values of continuing 4 bits in this sequence are all different, i.e., they provide all the values from 0 to 15.